New version of adet (V1.5) and READEME.pdf

9 dezembro 2020, 01:13 • Paulo Flores

Due to a bug on the adet code, the average determinant value was incorrect computed (it was divided by 8). Thank you Gonçalo Mão-Cheia for pointing out this problem.

Therefore, there is an updated adet zip file with a correct version (v1.5) of the program adet, adet.exe and a refreshed sd765.iter and README.pdf files.

New version of adet and READEME.pdf

2 dezembro 2020, 01:25 • Paulo Flores

Due to a bug on the adet code, the identification of the larger 1-norm matrix was incorrect. Thank you Miguel Reis for pointing out this problem.

Therefore, there is an updated adet zip file with a correct version (v1.3) of the program adet, adet.exe and a refreshed sd765.iter and README.pdf files.

Note that students should generate the files .dat and .itr on the same platform/OS that will be used for comparison of the results (expected vs read from the FPGA).
On Linux use adet and on Windows use adet.exe, for both generating and comparing values.

Files update for project lab.3

24 novembro 2020, 08:20 • Paulo Flores

The laboratories section was updated with files for the top_circuit (where the designed circuit should be included) and for the program adet (which generate random INIY_ data for the input memory and compare the results read from the FPGA with expected values).

Constraint file for Lab2

8 novembro 2020, 19:12 • Paulo Flores

Due to problems noted by some students, regarding the mismatching results from Behavioral and Post-Implementation Timing simulations, a constraints file for this laboratory project was upload into the Laboratories section (Lab2_Constraints.xdc).

This file impose constraints on the paths from the Input Ports to Internal Sequential Cell and from Internal Sequential Cell to the Output Ports. It also assign FPGA pins to top circuit signals.

Students should use this constraint file and change it according to the project developed. Hopefully, this will highlight some timing violations that were not previously detected and could interfere with simulations results.

Changes on classes next Wednesday and lab files update

25 outubro 2020, 20:20 • Paulo Flores

The Laboratories section was updated with VHDL files for several input memories (memIN) and the output memory (memOUT).
There is also a pdf file with some notes about the implementation and demo of project L2 - Architectural Synthesis.
The project script of Matrix and Determinant Computation was updated (new version 2020-10-25). Corrections were made on item 3, regarding size of inputs (16 bits) and name of the data bus of the output memory (dataOUT).

Due to medical appointment the classes (theoretical and laboratory) of the next Wednesday, October 28, 2020, will not be taught at the scheduled time. Therefore, the laboratory class will be anticipated to the same day, Wednesday, October 28, from 12:30 to 14:00 on LSD2. The theoretical class will be reschedule in a future date (if necessary).