L3 - Average Determinant (Digital System Design)

Project development on weeks 9 to 13 (labs classes form November 18 until December 18) with board demo, report until week 13..

• Average Determinant
  
  
• adet-QK95C3.zip -  adet-QKAJS7.zip - adet-QKOT7N.zip - adet-QL1S6K.zip - adet-QL5CPX.zip (V1.6)
  Program to generate initialization INIT_xx for the input memory (.dat) and a corresponding file (.itr) with all parameters values, the expected results and the partial values computed by the algorithm. This program is also used to check the correctness of the values read from the development board.
  See the README.pdf file for more details.
  
  
• top_cir-QKAJS7.zip
  Top circuit with the memories and UART for data transfer from the Basys3 board to the PC. The students should replace the example circuit,vhd  with the appropriated VHDL description to execute  the Average Determinant algorithm.
  

L2 - Architectural Synthesis (scheduling and resource sharing)

Architectural Synthesis (scheduling and resource sharing): development from week 5 to 8 (labs classes from October 21 until November 13), simulation demo and report until week 8.

• Matrix and Determinant Computation (new version 2020-10-25)
• Matrix and Determinant Computation
• Notes on Project Lab 2
• Lab2_Constraints.xdc
  

Examples of VHDL for the input memory (memIN) and the output memory (memOUT):

• Small input numbers (limited to 6, 8 and 10 bits):
  
  • memIN06b,vhd
  • memIN08b.vhd
  • memIN10b,vhd
    

• Large input numbers (16 bits):
  
  • memIN1.vhd
  • memIN2.vhd
  • memIN3.vhd
  • memIN4.vhd
  • memIN5.vhd

• memOUT.vhd
  
  
• memIN_tb.vhd
  

L1 - Simple ALU

Project development on weeks 3 and 4 (labs classes from October 7 until October 16), board demo and report on week 4.

• Simple Calculator

L0 - A Tutorial

A Tutorial introducing the Xilinx Vivado design tool and the development board Basys 3. (on week 2)

• Introduction Lab Guide
• Archive with lab files
• Basys3 Board Manual

Lab Projects

L0 - A Tutorial introducing the Xilinx Vivado design tool and the development board Basys 3. (on week 2)

L1 - Simple ALU: development on weeks 3 and 4 (labs classes from October 7 until October 16), board demo and report on week 4.

L2 - Architectural Synthesis (scheduling and resource sharing): development from week 5 to 7 (labs classes from October 21 until November 6), simulation demo and report until week 8.

L3 - Digital System Design: development from week 9 to 13 (labs classes form November 18 until December 18), board demo, report until week 13.