Constraint file for Lab2

8 novembro 2020, 19:12 • Paulo Flores

Due to problems noted by some students, regarding the mismatching results from Behavioral and Post-Implementation Timing simulations, a constraints file for this laboratory project was upload into the Laboratories section (Lab2_Constraints.xdc).

This file impose constraints on the paths from the Input Ports to Internal Sequential Cell and from Internal Sequential Cell to the Output Ports. It also assign FPGA pins to top circuit signals.

Students should use this constraint file and change it according to the project developed. Hopefully, this will highlight some timing violations that were not previously detected and could interfere with simulations results.