L3 - Best Line Selection (Digital System Design)

Project development on weeks 9 to 13 (labs classes form November 11 until December 9) with board demo, report until week 14.

• Best Line Selection

• top_cir_v1.zip - Top circuit with the memories and UART for data transfer from the Basys3 board to the PC. The students should replace the example circuit,vhd  with the appropriated VHDL description to execute  the Best Line Selection algorithm.
• bls_V1.zip
  bls-Q1N458.zip
  bls-Q20MEC.zip  -  Program to generate initialization INIT_xx for the input memory (.dat) and a corresponding file (.itr) with all parameters values, the expected results and the partial values computed by the algorithm. This program is also used to check the correctness of the values read from the development board.
  See the README.txt file for more details.
• MEMin3.zip - Zip with of the output of the program bls for the memories given as example for debugging on the top_cir_v1.zip
  

L2 - Architectural Synthesis (scheduling and resource sharing)

Architectural Synthesis (scheduling and resource sharing): development from week 6 to 9 (labs classes from October 16 until November 1), simulation demo and report until week 9.

• Average Computation
• Notes on Project Lab 2
  

Examples of VHDL for the input memory memIN and the output memory:

• Memory Organization
• memIN1.vhd  - Soluções com erros
  
• memOUT.vhd
• memIN_tb.vhd
  
  
• memIN1ok.vhd
  
• memIN2.vhd
• memIN3.vhd
• memIN4.vhd
• memINf.vhd
  

L1 - Simple ALU

Project development on weeks 3 and 4 (labs classes from October 2 until October 11), board demo and report on week 4.

• Simple Calculator
  

L0 - A Tutorial

A Tutorial introducing the Xilinx Vivado design tool and the development board Basys 3. (on week 2)

• Introduction Lab Guide
• Archive with lab files
• Basys3 Board Manual

Lab Projects

L0 - A Tutorial introducing the Xilinx Vivado design tool and the development board Basys 3. (on week 2)

L1 - Simple ALU: development on weeks 3 and 4 (labs classes from October 2 until October 11), board demo and report on week 4.

L2 - Architectural Synthesis (scheduling and resource sharing): development from week 5 to 7 (labs classes from October 16 until November 1), simulation demo and report until week 8.

L3 - Digital System Design: development from week 9 to 13 (labs classes form November 13 until December 13), board demo, report until week 14.