Hardware Debugging

22 março 2019, 14:00 • Horácio Neto

In-System Logic Design Debugging.
Probing phase steps. Insertion of debug cores. Setting up debug. Integrated Logic Analyser options.
Test in Hardware.

HW / SW co-processing architecture (1)

20 março 2019, 17:00 • Horácio Neto

Design and implementation of an embedded system with a uniprocessor and an hardware accelerator.

HW IP Simulation

20 março 2019, 15:30 • Horácio Neto

Design and Simulation Flow.
VHDL testbenchs specific for simulation of integer matrix product
Waveform Visualization.

Introduction to the Vivado Design Suite (3)

15 março 2019, 15:30 • Horácio Neto

Introductory Lab

HW/SW System using GP0.and AXI-Stream IP

15 março 2019, 14:00 • Horácio Neto

AXI-Stream FIFO
HW/SW System using GP0.
Software Drivers.