Planeamento

Aulas Teóricas

Course Presentation

Presentation of the course.

Objectives, program, planning and classes, and evaluation method.

Introduction to Multiprocessors in FPGAs

FPGA-based Multiprocessors

Cores from FPGA Companies

Embedded System Design Flow on Zynq

Zynq Architecture

Zynq All Programmable SoC (AP SoC)
Zynq AP SoC Processing System (PS)
Processor Peripherals
Clock Features
AXI Interfaces

Intro to FPGA

Introduction to programmable logic devices and FPGAs.

Artix-7 architecture and main elements.

Adding PL Hardware to the Embedded System

Communication between PS and PL
Base IP with AXI-Lite Interface
Adding IP to the Zynq System
Evaluating resource usage and timing

Custom HW components

Codesign Development
Amdahl's law and Hardware Speedup
HW/SW Communication
Performance Comparisons
Stream-Based Interfaces

Basic Hardware Architecture

Register-Transfer Level Methodology
FSMD = control unit + datapath
Algorithm to hardware: direct “dataflow” implementation, datapath with shared operators.

Stream-Based IP

Stream-Based Datapath Unit.
Adding BRAM IP

FSM of Stream-Based IP

AXI-Stream Control Unit.

HW/SW System using GP0.and AXI-Stream IP

AXI-Stream FIFO
HW/SW System using GP0.
Software Drivers.

HW IP Simulation

Design and Simulation Flow.
VHDL testbenchs specific for simulation of integer matrix product
Waveform Visualization.

Hardware Debugging

In-System Logic Design Debugging.
Probing phase steps. Insertion of debug cores. Setting up debug. Integrated Logic Analyser options.
Test in Hardware.

Floating-Point IP

Floating-Point IP cores.
Floating point standard formats and main arithmetic block components.
Multiplier and Accumulator cores. Non-blocking and Blocking modes.

Floating-Point IP (2)

Matrix-Product Floating-Point IP core.
Floating-Point HW Simulation.
Software kernel for HW/SW design.
Packaging IP.

Direct Memory Access

Using Direct Memory Access to data shared between SW and HW.
AXI DMA IP.
Connecting the AXI-Stream HW IP.
Example Application.

Matprod IP simple DMA-based Architecture

Interfacing the Matprod AXI-Stream IP with a DMA AXI Component.

Zynq Memory Resources

On-chip memory (OCM): RAM.
DDR3 external memory.
APU Memory Hierarchy, L1 and L2 caches.
OCM / DDR Address Map.
Linker Script – Use Example.
Shared Memory and Cache Issues.
Cortex A9 Processor Cache Functions.

Dual Microprocessor System Design

Software Development for dual ARM Zynq platform.
Configuration management.
Shared memory management.
Dual Matrix-Product Test Application.

Architectures for PL Accelerators

A multi-processor for cluster analysis - design example 1.
K-means clustering application.
Architecture, processing elements and data movements.
Implementation, resource utilization and performance analysis.

Multi-processor for sparse matrix applications - design example 2.
Architecture, processing elements and data movements.
Implementation, resource utilization and performance analysis.

AXI bus

Advanced eXtensible Interface (AXI) bus.
Basic AXI Transactions. AXI-Full, AXI-Lite and AXI-Stream Signals.
AXI Interconnect block.
AXI-Lite vs. AXI-Stream.

Networks-on-Chip - Advanced Bus Architectures

Bus based Communication Architectures. Main Topologies, Decoding and Arbitration.
Standard Bus Architectures.
Network-on-Chip (NoC). Definitions and Terminology. Generic Routers. Switching strategies.
Intel 80-Tile Teraflop NoC design.

Summary on HW/SW Codesign

Factors driving codesign.
HW vs. SW Performance trade-offs.
Abstraction Levels for codesign models.
Codesign Methodology.
State of Codesign Technology.
SystemC for Co-Specification.

Hardware (Software) Challenges

C-to-Hardware design tools.
High-Level Synthesis versus OpenCL.

Support to Final Project

Support to the completion of the final project (in LSD2).

Support to Final Project

Support to the completion of the final project (in LSD2).

Support to Final Project

Support to the completion of the final project (in LSD2).

Support to Final Project

Support to the completion of the final project (in LSD2).