Introduction to the the Vivado Design Suite (3)

11 março 2016, 15:30 • Horácio Neto

HW IP Simulation

11 março 2016, 14:00 • Horácio Neto

Design and Simulation Flow.
VHDL testbenchs specific for simulation.
Waveform Visualization.

Introduction to the the Vivado Design Suite (3)

9 março 2016, 17:00 • Horácio Neto

Simple Multiply-Accumulate IP

9 março 2016, 15:30 • Horácio Neto

Designing a Multiply-Accumulate hardware component to execute vector dot products.
VHDL Specification of the Unit: Simple Registers, Accumulator and Arithmetic Operators.
Packages for Numeric Operations.
Component Definition and Instantiation.
Control Signal Generation from AXI_Lite interface.

Introduction to the the Vivado Design Suite (2)

4 março 2016, 15:30 • Horácio Neto