Basic Hardware Architecture

4 março 2016, 14:00 • Horácio Neto

Register-Transfer Level Methodology
FSMD = control unit + datapath
Algorithm to hardware: direct “dataflow” implementation, datapath with shared operators.

Introduction to the the Vivado Design Suite (2)

2 março 2016, 17:00 • Horácio Neto

Adding PL Hardware to the Embedded System

2 março 2016, 15:30 • Horácio Neto

Communication between PS and PL
Managing IP components
Creating base IP with AXI-Lite Interface
Add IP to the Zynq System
Evaluating resource usage and timing

Introduction to the the Vivado Design Suite

26 fevereiro 2016, 15:30 • Horácio Neto

Zynq Architecture

26 fevereiro 2016, 14:00 • Horácio Neto

Zynq All Programmable SoC (AP SoC)
Zynq AP SoC Processing System (PS)
Processor Peripherals
Clock Features
AXI Interfaces