Sumários
Caches
30 abril 2015, 15:30 • Leonel Augusto Pires Seabra de Sousa
Cache
memories:
- Revision of basic cache memories
- Data replacement policies and Write Policies
- Hierarchical cache systems
- Optimizing caches: software and hardware techniques
Description RTL of the pipeline uRISC processor
30 abril 2015, 11:00 • Leonel Augusto Pires Seabra de Sousa
RTL Description of the uRISC processor: pipeline operation
Description RTL of the pipeline uRISC processor
28 abril 2015, 15:30 • Leonel Augusto Pires Seabra de Sousa
RTL Description of the uRISC processor: pipeline operation
Memory technologies
28 abril 2015, 14:00 • Leonel Augusto Pires Seabra de Sousa
Memory
technologies:
- SRAM
- DRAM
- SDRAM
- DDR/DDR2/DDR3
- FLASH
Description RTL of the pipeline uRISC processor
27 abril 2015, 15:30 • Leonel Augusto Pires Seabra de Sousa
RTL Description of the uRISC processor: pipeline operation