Sumários
Pipelining and Processor Performance
5 março 2015, 15:30 • Leonel Augusto Pires Seabra de Sousa
Revision
- Single cycle processor
- Multi cycle processor
Processor pipelining
- Instruction flow in a pipeline processor
- Execution conflicts
Evaluating processor performance
Behavioral Description of the uRISC processor
5 março 2015, 11:00 • Leonel Augusto Pires Seabra de Sousa
Behavioral Description of the uRISC processor: multicycle approach
Behavioral Description of the uRISC processor
3 março 2015, 15:30 • Leonel Augusto Pires Seabra de Sousa
Behavioral Description of the uRISC processor: multicycle approach
Introduction to VHDL
3 março 2015, 14:00 • Leonel Augusto Pires Seabra de Sousa
Hardware Description Languages (HDL)
- VHDL: Very High Speed Integrated Circuits (VHSIC) Hardware Description Language
- Typical VHDL structure
- General Tips and tricks
- Examples
Behavioral Description of the uRISC processor
2 março 2015, 15:30 • Leonel Augusto Pires Seabra de Sousa
Behavioral Description of the uRISC processor: multicycle approach