28 Janeiro 2019, 16:58 • Horácio Neto
Lectures will begin on wednesday, Feb-20 15H30 at EA3.
Labs will begin on the week of Feb-27.
Each group may have up to 2 students. Lab inscriptions will be processed via fenix-groups, starting after the first lecture class on Feb-20. Details will be provided during the course presentation.
The course main objective is the design and implementation of hardware/software systems of medium complexity using SoC FPGAs.
The students are assumed to have a basic
understanding of processor-based systems, digital design, and C programming, as acquired in the MEEC 1st cycle.
The course will be design-focused using the Zynq-7000 All Programmable SoC devices,
which support advanced design of hardware/software embedded systems, by
integrating in the same chip a dual-core ARM processor-based software
system with a FPGA-based hardware system.
The hardware components will be developed using a HLS-based flow from a C hardware specification. The advantages and problems of using C-based hardware specifications are well illustrated in this Xilinx video on an image filter design.
(A RTL-based design flow from a VHDL specification may be used optionally, but will not be emphasized and HDL experience is not required)