Sumários
Introduction to FPGAs and Series-7 devices. Baseline Application for Project P1.
15 maio 2023, 14:00 • Horácio Neto
Introduction to programmable logic devices and FPGAs.
Artix-7 architecture and main elements.
Memory resource usage in HW components
Efficiency tradeoffs according to specific FPGA primitives
High-Level Synthesis of AXI-Lite IP (2)
11 maio 2023, 10:00 • Horácio Neto
High-Level Synthesis of AXI-Lite IP (slides 79-95)
HW specific data types:
HLS Arbitrary Precision Types .
Selecting the appropriate type and bit-width of the datapath signals .
Packing more than 1 data element per bus word.
Baseline Application for Project P1.
Project 1 assignment.
Convolution 2D.
Images dataset.
Baseline C application.
Introduction to the Vitis/Vivado Design Suite (2)
10 maio 2023, 11:00 • Horácio Neto
Introductory Lab
Introduction to the Vitis/Vivado Design Suite (2)
9 maio 2023, 10:30 • Horácio Neto