Doctoral Degree in Electrical and Computer Engineering of IST/UL
2. Filipe Azevedo, “Generative AI Solutions for Analog Integrated Circuits Design”. Ongoing (expected in 2026).
1. António Gusmão, “Deep Learning Techniques for End-to-end Deep Nanometer Analog and Radio Frequency Integrated Circuit Design Automation”. Ongoing (expected in 2025).
Master's Degree in Electrical and Computer Engineering / Electronics Engineering of IST/UL
19. Pedro Paiva, “Optimization Speed-Up using Machine/Deep Learning”. Ongoing (expected in 2025).
18. Carlos Almeida, “Convolutional Variational Autoencoder for Integrated Circuits Layout”. Ongoing (expected in 2025).
17. João Salbany, “Drawing Interconnects with Generative Artificial Intelligence”. Ongoing (expected in 2025).
16. Gonçalo Santos, “Assisting Interconnects’ Drawing with Convolutional Neural Networks”. Ongoing (expected in 2025).
15. Vasco Ferreira, “Design Space Exploration and Frontiers between Low-Power Gate-Driven and Bulk-Driven Integrated Circuit Topologies”. Ongoing (expected in 2025).
14. José Costa, “Agents that Design Circuits: Reinforcement Learning approach to Analog Integrated Circuit Design Automation”. Ongoing (expected in 2025).
13. Daniel Ernesto, “Ensemble Machine/Deep Learning for Performance Prediction”. Ongoing (expected in 2025).
12. Diogo Peneda, “Improving Sampling Efficiency of Multi-Net Multi-Terminal Analog Integrated Circuit Routing with Machine Learning”. Ongoing (expected in 2025).
11. Pedro Eid, “Generative Artificial Intelligence for Analog Integrated Circuit Design Automation”. Ongoing (expected in 2024).
10. Duarte Marques, “Layout design automation for power devices”. Ongoing (expected in 2024).
9. João Domingues, “Accelerating Voltage-Controlled Oscillator Sizing Optimizations with a Convergence Classifier & Frequency Guess Predictor”. Concluded in Oct. 2021.
8. Pedro Vaz, “Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator using Deep ANNs”. Concluded in Oct. 2021.
7. Pedro Alves, “ANN-based Floorplan Recommender for Analog IC Building Blocks with Broader Topological Constraints Coverage”. Concluded in Oct. 2021.
6. António Gusmão, “Semi-Supervised Artificial Neural Networks towards Push-Button Analog IC Placement”. Concluded in Oct. 2019.
5. Daniel Guerra, “On the Exploration of Automatic Analog Integrated Circuit Placement using Neural Networks”. Concluded in Oct. 2018.
4. Pedro Biscaia, “EDA to the cloud –a case study to increase both effectiveness and user experience of EDA tools”. Concluded in Oct. 2018.
3. João Rosa, “Using Artificial Neural Networks to Size Analog Integrated Circuits”. Concluded in June 2018.
2. Tiago Pessoa, “Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel”. Concluded in Nov. 2017.
1. Bruno Cardoso, “AIDA-PEx: Parasitic Extraction on Layout-Aware Analog Integrated Circuit Sizing”. Concluded in May 2015.