### Planeamento

### Aulas Teóricas

## Presentation and Introduction

Course presentation.

Introduction to the digital systems design flow.

## VHDL

Introduction to VHDL (1-19)

Simple circuit example to be implemented in the Introductory Lab.

## VHDL (2)

Introduction to VHDL (20-45)

VHDL Language Constructs

## VHDL (3)

Introduction to VHDL (46-76)

VHDL Coding Examples

## VHDL (4)

Introduction to VHDL (77-end)

Arithmetic Operators. Use of Generics for Component Parameterization.Generate Statements.

Simulation: models and delays.

## Architectural Synthesis - Introduction to RTL

Introduction to RTL Design.

Design Flow and Main Design Tasks

Register-Transfer Level Methodology

Direct “dataflow” implementation

Resource Sharaing Datapath Example

Architectural Synthesis Tasks

## Architectural Synthesis

Architectural Synthesis Example.

Scheduling Techniques

## Architectural Synthesis (2)

Alocation and Binding Techniques.

Operator and Register Sharing.

Architecture Implementation.

## Architectural Synthesis (3)

Architectural Optimization by Pipelining.

Hierarchical control structures.

Architectural Optimization - final summary.

## Logic Synthesis

Sequential Logic Synthesis.

Synchronization of FSMs and Control Pipelining..

Microcode based Control Units.

FSM Enconding main options.

## Logic Synthesis (2)

Vivado Design Flow.

Synthesis Settings.

Timing Analysis.

## Logic Synthesis / FPGA Devices

Flip-Flop Retiming.

Multi-level synthesis and Technology Mapping.

FPGA Devices.

Device Technologies - In the “fab”; In the “field”

Basic FPGA Model

Artix-7 Family Architecture: Configurable Logic Blocks

## FPGA Devices (2)

36-Kbit Block RAM

DSP Blocks

## FPGA Arithmetic (1)

FPGA Carry chains.

Adder/Subtractor Implementations and Precision.

Multi-Operand Adders.

## FPGA Arithmetic (2)

Multiplier Implementations. Precision and Truncation of Result.

DSP48E1 "Multiplier" Blocks. Pipelining.

Booth Multiplication.

## FPGA Arithmetic (3)

Divider Implementations.

Fixed-point
arithmetic.

## FPGA Arithmetic (4)

Floating-point
arithmetic.

Decimal arithmetic.

Implementation of elementary functions.

## IP Blocks

Using Xilinx IP Catalog.

Block
Memory Generator application example.

BRAM initialization using a Coefficient
File.

IP instantiation templates.

## Clock Distribution and Sinchronization

Clocking Architecture in 7 series FPGAs.

Timing
Issues and constraints on Clock Skew.

Phase-Locked
Loop (PLL) Blocks: features and usage.

Clock
Wizard.

## FPGA Overview

FPGA concluding overview.

Xilinx and Altera FPGAs: Configurable Logic Blocks, Block RAMs, Embedded Multipliers, Hard- and Soft-Microprocessor Cores.

Microsemi SmartFusion and Igloo FPGAs.

SoC FPGAs.

## Asynchronous Circuits

Self-timed and asynchronous design.

Self-timed micropipelines.

GALS - Globally Asynchronous Locally Synchronous Systems.

Dual-Clock FIFOs as an efficient interface between different clock domains.

## FPGA IO Interface

FPGA IO Interface: demonstration example.

Dumping BRAM memory contents in simulation.

## Support to Final Project

Support to Final Project (LSD2)

## Support to Final Project

Support to Final Project (LSD2)

## Support to Final Project

Support to Final Project (LSD2)