Planeamento

Aulas Teóricas

Apresentação e Introdução

Informações sobre a disciplina.

VHDL

VHDL (1-11)

VHDL

VHDL (11-33)

VHDL

VHDL (33-51)

VHDL

VHDL (51-72)

Introduction to RTL

Introduction to RTL (1-18)

Architectural Synthesis

Architectural Synthesis  (1 - 21)

Architectural Synthesis

Architectural Synthesis  (21 - 42)

Architectural Synthesis

Architectural Synthesis  (42 - 65)

Architectural Synthesis and Logic Synthesis

Architectural Synthesis  (61 - 68)
Introduction to the use of BRAM (1 -12)
Logic Synthesis (1 - 16) 

Logic Synthesis

Logic Synthesis (14 - 53) 

FPGA devices

FPGA devices (fpga_A 1-29)

FPGA devices

FPGA devices (fpga_A 30-49)

FPGA devices

FPGA devices (fpga_A 50-71)

FPGA devices

FPGA devices (fgpa_B 1-34)

Aula de apoio ao projecto

Aula de apoio ao projecto:

  • Interface de comunicação
  • Debug com a placa de desenvolvimento

FPGA devices

FPGA devices (fpga_C 1-28)

Arithmetic on FPGAs, Number representation

Arithemetic on FPGAs (5fpga_C 28-38)
Number representation (6numbers 1-8)

Number representation

Number representation (6numbers 8-18)

 

Temporal synchronization

Temporal synchronization (7fpgaC 1-23 + 7xilinx_design.pdf 1-14 )

Embedded processing

Embedded processing (8picoblazer 1-24)

Supporting classes for lab assignment

Supporting classes for the 3rd laboratory assignment/

Other programmable logic devices

Other programmable logic devices (9fpga-others 1-48)

Asynchronous design

Asynchronous design (10asynchronous 1-17)

Supporting classes for lab assignment

Supporting classes for the 3rd laboratory assignment  (LSD)

Supporting classes for lab assignment

Supporting classes for the 3rd laboratory assignment  (LSD)

Supporting classes for lab assignment

Supporting classes for the 3rd laboratory assignment  (LSD)

Supporting classes for lab assignment

Supporting classes for the 3rd laboratory assignment  (LSD)