Apresentação e Introdução
Informações sobre a UC.
Introdução ao fluxo de projecto de sistemas digitais.
Introduction to VHDL (1-16)
Introduction to VHDL (17-40)
Introduction to VHDL (41-71)
Introduction to VHDL (72-end)
Introduction to RTL
Introduction to RTL (1-19)
Design Flow and Main Design Tasks
Register-Transfer Level Methodology
Direct “dataflow” implementation
Resource Sharaing Datapath Example
Architectural Synthesis (1 - 22)
Architectural Synthesis Tasks: Resource Selection / Allocation, Scheduling, Resource Binding
Architectural Synthesis Example (Introduction)
Architectural Synthesis (2)
Architectural Synthesis (23 - 50)
ASAP and ALAP Scheduling.
List Scheduling: Priority on the Critical Path; Priority on the Mobility.
Detailed Architectural Implementation
Architectural Synthesis (3)
Architectural Synthesis (51 - 70)
Architectural Optimization by Pipelining.
Hierarchical control structures.
Architectural Optimization - final summary.
Logic Synthesis (1 - 25)
Sequential Logic Synthesis.
Synchronization of FSMs.
Microcode based Control Units.
FSM Enconding main options.
Logic Synthesis (26 - 45)
ISE Design Flow.
Synthesis Contraints Objectives.
Optimization Timing Domains.
Logic Synthesis (46 - 70)
Device Resource Utilization.
Speed Optimization Under Area Constraint.
Implementation Overview for FPGAs.
FPGA Devices (1 - 29)
Device Technologies - In the “fab”; In the “field”
Basic FPGA Model
Spartan-3 Family Architecture
FPGA Devices (30 - 47)
LUT Resources in a Slice
LUTs as Shift Registers
Dedicated carry logic
Intro to 18-Kbit Block RAM
FPGA Devices (48 - 67)
Block RAM Memory: Organizations and Aspect Ratios.
Dual-Port RAM Components.
Port Address Mapping.
Inferring and Initializing Block RAM. Write Modes.
FPGA Devices and USB to FPGA interface
FPGA Devices (68 - 71)
FPGA Routing Resources and Global Clock Network.
Interface USB to FPGA (1-11)
FPGA Arithmetic (1)
FPGA Arithmetic (1 - 22)
FPGA Carry chains.
FPGA Arithmetic (2)
FPGA Arithmetic (23 - 45)
FPGA Arithmetic (3)
FPGA Arithmetic (46 - 64)
FPGA Arithmetic (4)
FPGA Arithmetic (65 - 87)
Fixed-point Representation and Arithmetic.
Introduction to floating-point representation.
FPGA Arithmetic (5)
FPGA Arithmetic (86 - 105)
Table-based approximation of Elementary Functions.
Clock Distribution and Sinchronization
Clock distribution and sinchronization (1-24)
Global Clock Network
Constraints on Clock Skew
Digital Clock Managers
FPGA Overview (1)
FPGA Overview (1-24)
XILINX FPGAs: Configurable Logic Blocks, Block RAMs, Embedded Multipliers, Hard- and Soft-Microprocessor Cores.
FPGA Overview (2)
FPGA Overview (25-54)
Altera FPGAs: Logic, Array and Memory Blocks. Soft-processor.
Example of Actel FPGAs.
Run-time reconfiguration and the virtual hardware concept.
Asynchronous Circuits (1-16)
Self-timed and asynchronous design.
GALS - Globally Asynchronous Locally Synchronous Systems.
Dual-Clock FIFOs as an efficient interface between different clock domains.