Exams
Exams
- 1st class - Exercises I: Performance Metrics
- 2nd class - Exercises II: Logic Architecture
- 3rd class - Exercises III: Pipelining
- 4th class - Exercises IV: Pipelining and Caches
- 5th class - Exercises V: Caches
- 6th class - Exercises VI - Virtual Memory
- 7th class - Exercises VII - IO and Storage
- 8th class - Exercises VIII - Multiprocessors
Slides from theoretical classes
- 10th class: Control Hazards
- 11th class: VLIW and Superscalar
- 12th class: Memory System
- 13th class: Improving Cache Performance
- 14th and 15th class: Optimizing Cache Usage
- 16th class: Virtual Memory
- 17th class: Virtual Machines
- 18th class: IO System
- 19th and 20th class: Disk Storage and Dependability
- 1st class: Course Information
- 21st class: Analog-Digital Interface
- 22nd class: Embedded Architectures
- 23rd and 24th class: Thread-level Parallelism
- 25th class: Vector Processing
- 26th class: Message-Passing Multiprocessors
- 2nd class: Metrics and Performance
- 3rd class: Instruction Set Architecture
- 4th class: Control Instructions
- 5th class: Role of the Compiler
- 6th class: Computer Arithmetic
- 7th class: The MIPS Processor
- 8th class: The MIPS Pipeline
- 9th class: Data Hazards
- 10th class: Control Hazards
- 11th class: VLIW and Superscalar
- 12th class: Memory System
- 13th class: Improving Cache Performance
- 14th and 15th class: Optimizing Cache Usage
- 16th class: Virtual Memory
- 17th class: Virtual Machines
- 18th class: IO System
- 19th and 20th class: Disk Storage and Dependability
- 1st class: Course Information
- 21st class: Analog-Digital Interface
- 22nd class: Embedded Architectures
- 23rd and 24th class: Thread-level Parallelism
- 25th class: Vector Processing
- 26th class: Message-Passing Multiprocessors
- 2nd class: Metrics and Performance
- 3rd class: Instruction Set Architecture
- 4th class: Control Instructions
- 5th class: Role of the Compiler
- 6th class: Computer Arithmetic
- 7th class: The MIPS Processor
- 8th class: The MIPS Pipeline
- 9th class: Data Hazards