Course Plan

• Course Plan (updated on January 26th, 2026)

Required Background

• Appendix 1 - RISC-V Instruction Set Architecture (revision)
• Instruction Set Architecture (revision)
• RISC-V Reference Card
• Overview of cache memories (will be revised and further addressed in theoretical classes)

Note: the actual instructions are not to be memorised; the RISC-V reference card can be used in all evaluation points (labs, mini-tests, exam).

Classes:

• 00 - Course outline and evaluation guide
• 01 - Introduction to Computer Architectures
• 02a - Pipelined Processor Architectures
• 02b - Branch Prediction
• 03 - Static Exploitation of ILP <-- End of material to be evaluated in the First Test
• 04 - Dynamic Exploitation of ILP
• 05 - Overview of modern processor core architectures  <-- End of material to be evaluated in the Second Test
• 06 - SIMD/vector extensions
• 07 - GPU Architectures
• 08 - General-Purpose Computing on GPUs (CUDA)
• 09 - Cache Memories
• 10 - Virtual Memory  <-- End of material to be evaluated in the Third Test
• 11 - Multiprocessors