FenixEdu™

Course Presentation

Aula 1

Presentation of the course.

Objectives, program, planning and classes, and evaluation method.

Introduction to Multiprocessors in FPGAs

Aula 2

FPGA-based Multiprocessors

Cores from FPGA Companies

Embedded System Design Flow on Zynq

Zynq Architecture

Aula 3

Zynq All Programmable SoC (AP SoC)
Zynq AP SoC Processing System (PS)
Processor Peripherals
Clock Features
AXI Interfaces

Intro to FPGA

Aula 4

Introduction to programmable logic devices and FPGAs.

Artix-7 architecture and main elements.

Adding PL Hardware to the Embedded System

Aula 5

High-Level Synthesis of AXI-Lite IP

Specification of the AXI-Lite Interface

AXI4-Lite I/O Addresses

HLS Synthesis Results

SW+HW Matrix-Product Kernel

Custom HW components

Aula 6

Codesign Development
Amdahl's law and Hardware Speedup
HW/SW Communication
Performance Comparisons
Stream-Based Interfaces

Stream-Based IP

Aula 7

High-Level Synthesis of AXI-Stream IP
HLS Streams

AXI-Stream matrix-vector poduct IP

HW/SW System using GP0.and AXI-Stream IP

Aula 8

AXI-Stream FIFO
HW/SW System using GP0.
Software Drivers.

HW IP Simulation

Aula 9

Design and Simulation Flow.
VHDL testbenchs specific for simulation of integer matrix product
Waveform Visualization.

Hardware Debugging

Aula 10

In-System Logic Design Debugging.
Probing phase steps. Insertion of debug cores. Setting up debug. Integrated Logic Analyser options.
Test in Hardware.

Floating-Point IP

Aula 11

Floating-Point IP cores.
Floating point standard formats and main arithmetic block components.
Multiplier and Adder cores. Non-blocking and Blocking modes.
HLS specification of a Floating-Point AXI-Stream IP

Fixed-point Operators

Aula 12

Fixed-Point representation and arithmetic.

HLS Fixed-Point Types. Quantization, overflow and arithmetic operators.

Fixed-point accumulator

Aula 13

Fixed-point accumulator
Accumulator Precision
HLS Accumulator Specification
Floating-point to fixed-point and fixed-point to floating-point converters

Direct Memory Access

Aula 14

Using Direct Memory Access to data shared between SW and HW.
AXI DMA IP.
Connecting the AXI-Stream HW IP.
Example Application.

Matprod IP simple DMA-based Architecture

Aula 15

Interfacing the Matprod AXI-Stream IP with a DMA AXI Component.

Zynq Memory Resources

Aula 16

On-chip memory (OCM): RAM.
DDR3 external memory.
APU Memory Hierarchy, L1 and L2 caches.
OCM / DDR Address Map.
Linker Script – Use Example.
Shared Memory and Cache Issues.
Cortex A9 Processor Cache Functions.

Dual Microprocessor System Design

Aula 17

Software Development for dual ARM Zynq platform.
Configuration management.
Shared memory management.
Dual Matrix-Product Test Application.

Support to Project Demonstration

Aula 18

Support to the completion of the first project (in LSD2).

Architectures for PL Accelerators

Aula 19

A multi-processor for cluster analysis - design example 1.
K-means clustering application.
Architecture, processing elements and data movements.
Implementation, resource utilization and performance analysis.

Multi-processor for sparse matrix applications - design example 2.
Architecture, processing elements and data movements.
Implementation, resource utilization and performance analysis.

A HW/SW architecture for equation solving by Jacobi iteration algorithm - example 3.
A HW/SW architecture for kNN classification - example 4.

AXI bus

Aula 20

Advanced eXtensible Interface (AXI) bus.
Basic AXI Transactions. AXI-Full, AXI-Lite and AXI-Stream Signals.
AXI Interconnect block.
AXI-Full vs. AXI-Lite vs. AXI-Stream.

Networks-on-Chip - Advanced Bus Architectures

Aula 21

Bus based Communication Architectures. Main Topologies, Decoding and Arbitration.
Standard Bus Architectures.
Network-on-Chip (NoC). Definitions and Terminology. Generic Routers. Switching strategies.
Intel 80-Tile Teraflop NoC design.

Summary on HW/SW CoDesign and Hardware (Software) Challenges

Aula 22

Factors driving codesign.
HW vs. SW Performance trade-offs.
Abstraction Levels for codesign models.
Codesign Methodology.
State of Codesign Technology.
SystemC for Co-Specification. C-to-Hardware design tools.
High-Level Synthesis versus OpenCL.
Upcoming Devices