Adding PL Hardware to the Embedded System

8 março 2017, 15:30 • Horácio Neto

Communication between PS and PL
Managing IP components
Creating base IP with AXI-Lite Interface
Add IP to the Zynq System
Evaluating resource usage and timing

Introduction to the the Vivado Design Suite

3 março 2017, 15:30 • Horácio Neto

Introductory Lab

Intro to FPGA

3 março 2017, 14:00 • Horácio Neto

Introduction to programmable logic devices and FPGAs.

Artix-7 architecture and main elements.

Introduction to the the Vivado Design Suite

1 março 2017, 17:00 • Horácio Neto

Introductory Lab

Zynq Architecture

1 março 2017, 15:30 • Horácio Neto

Zynq All Programmable SoC (AP SoC)
Zynq AP SoC Processing System (PS)
Processor Peripherals
Clock Features
AXI Interfaces