10 Dezembro 2013, 18:13 - Lucília Abreu
Abstract: Process corners, corner cases, worst case parameter sets, ...; there are a lot of myths about certain parameter sets that are supposed to capture some kind of measure for variability of a circuit manufactured in a semiconductor technology. But what are these corners really? How are they determined? How should the results of a worst-case simulation be interpreted? And how can I get an estimation of the yield, more specifically, the parametric yield? These are questions that every designer of analog and mixed-signal circuits is confronted with in his every-day life of designing complex circuits in ever-advancing technologies with ever-increasing transistor variability. The first part of the talk will give some answers.
Constraints are key elements of analog design automation: a mathematical optimization tool would not be applicable if it would not be provided with constraints to keep transistors in saturation, to take care of symmetrical sizing, for instance. Interestingly, the netlist of an analog circuit inherently can provide a lot of constraints. The second part of the talk presents a method to automatically extract constraints out of a given netlist. It consists of two parts. First, an analysis of the hierarchical structure of a circuit is described. Second, a signal path analysis is presented. Theoverall outcome are constraints for sizing and placement, as well as a construction plan for analog placement. It will be illustrated how to use this outcome in sizing and placement of analog circuits.
Bio: Helmut Graeb got his Dipl.-Ing., Dr.-Ing., and habilitation degrees from Technische Universitaet Muenchen in 1986, 1993 and 2008, respectively. He was with Siemens Corporation, Munich, from 1986 to 1987, where he was involved in the design of DRAMs. Since 1987, he has been with the Institute of Electronic Design Automation, TUM, where he has been the head of a research group since 1993. His research interests are in design automation for analog and mixed-signal circuits, with particular emphasis on Pareto optimization of analog circuits considering parameter tolerances, analog design for yield and
reliability, hierarchical sizing of analog circuits, analog/mixed signal test design, discrete sizing of analog circuits, structural analysis of analog and digital circuits, and analog layout synthesis. Dr. Graeb has, for instance, served as a Member of the Executive Committee of the ICCAD conference, as a Member or Chair of the Analog Program Subcommittees of the ICCAD, DAC, and D.A.T.E conferences, as Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II: ANALOG AND DIGITAL SIGNAL PROCESSING and IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, and as a Member of the Technical Advisory Board of MunEDA GmbH Munich, which he co-founded. He is a Senior Member of IEEE (CAS) and member of VDE (ITG). He was the recipient of the 2008 prize of the InformationTechnology Society (ITG) of the Association for Electrical, Electronic and Information Technologies (VDE), of the 2004 Best Teaching Award of the TUM EE Faculty Students Association, of the 3rd prize of the 1996 Munich Business Plan Contest.